Metal-Gated Junctionless Nanowire Transistors

Junctionless Nanowire Field-Effect Transistors (JNFETs), where the channel region is uniformly doped without the need for source-channel and drain-channel junctions or lateral doping abruptness, are considered an attractive alternative to conventional CMOS FETs. Previous theoretical and experimental works [1][2] on JNFETs have considered polysilicon gates and silicon-dioxide dielectric. However, with further scaling, JNFETs will suffer from deleterious effects of doped polysilicon such as high resistance, additional capacitance due to gate-oxide interface depletion, and incompatibility with high-κ dielectrics[3][4]. In this paper, novel metal-gated high-κ JNFETs (MJNFETs – Fig. 1) are investigated through detailed process and device simulations. These MJNFETs are also ideally suited for new types of nano-architectures such as N 3 ASICs [5] which utilize regular nanowire arrays with limited customization. In such nano-systems, the simplified device geometry in conjunction with a single-type FET circuit style [6] would imply that logic arrays could be patterned out of pre-doped SOI wafers without the need for any additional ion implantation. In the MJNFET, the material properties of the gate and channel wires in conjunction with the nanoscale dimensions enable FET-like switching characteristics without the need for engineered source/drain junctions or lateral doping abruptness. Depending on the work function of gate, the heavily doped channel region of junctionless transistor is fully depleted without the application of an external bias (normally-off device – Fig. 2A). As the gate voltage increases, the electron concentration in the channel region starts to increase until it reaches the doping concentration Nd, at which point the flat-band condition is reached (Figs. 2B – 2D). The workfunction requirement for the gate in MJNFETs is tuned to achieve full-channel depletion. Materials with higher (lower) workfunction than the doped semiconductor channel are expected to deplete n-type (p-type) channels. Fig. 3 shows the range of metal workfunctions[7] suitable for achieving n-and p-type FETs. This is in direct contrast to workfunction requirements for conventional FETs [3] (e.g. n-type MOSFETs would require workfunction < 4.6). The properties of MJNFETs were analyzed through detailed TCAD simulations [8]. The device structures were created using Synopsys Process considering detailed process effects such as implantation parameters, diffusion temperature, oxide growth etc. Given the nanowire dimensions under consideration, full 3-D simulations of the device structure are required. A quantum confinement model was used for modeling charge transport. The channel dimensions were 22nm (length) X 10nm (width) X 10nm (height). Channel doping was assumed to be n-type (2 X 10 19 …